int8 · Verilog · FPGA
Quantized networks on an Arduino UNO, in Verilog, and on a real FPGA, each checked bit-exact against a Python golden model. One of them is running live on this page: my int8 planner, balancing a pendulum.
Almost all the work in a neural network is int8 dot products. I build the hardware that does them, and check every answer bit for bit, against Python.
tiny-tensor-core · Verilog · ECP5
My 6,634-parameter MNIST network as a chip. Scroll, and the figure runs the real int8 weights through the same schedule as the Verilog, clock by clock.
One pixel per clock is broadcast to 32 multiply-accumulate lanes, each holding one neuron's weights. 6,272 MACs, 32 at a time.
No floats. Each accumulator becomes a 0–127 activation with one fixed-point multiply and a shift: (acc · 31,942 + B + 2²³) ≫ 24. The clamp at 0 is the ReLU.
The 32 activations stream into 10 accumulators, one per digit.
Ten compares, and out comes the digit. The Arduino UNO needed about 491,000 clocks for the same network; the predictions match on all 10,000 test images.
Lab · resistors → AVR → RTL → FPGA
Each project takes the one before it a level lower, and every one is checked against a golden model before it counts.
Open the planner bench →
01 · analog · breadboard
A neuron's weighted sum done by resistors instead of a processor. Inputs are voltages, weights are conductances, and Kirchhoff's current law does the multiply-accumulate.
02 · C · PyTorch · AVR
A digit classifier trained in PyTorch, quantized to int8 and run on an 8-bit microcontroller with no FPU. The weights stream from flash a byte at a time.
03 · Verilog · iCE40
NVIDIA's DP4A instruction in Verilog: four int8 multiplies summed into a 32-bit accumulator in one operation, with one 9×9 multiplier covering every sign mode.
04 · Verilog · ECP5
The whole MNIST network as a chip: 32 parallel MAC lanes, integer-only requantization between layers, and an argmax that outputs the digit.
05 · Verilog · CUDA · Tang Nano 20K
Sampling-based model-predictive control with the rollouts in hardware: every tick, 32 int8 lanes imagine 32 futures of a pendulum and hand back the best plan.
int8-rollout-engine · on the board · Oct 14, 2026
The 8-lane planner went onto a Tang Nano 20K. It ran the right sequence, with the clock count exact every time, and got 0 of 20 answers right.
A/B builds narrowed it down. Turning off the carry chains changed nothing. Building the multipliers from LUTs instead of the chip's DSP blocks made it bit-exact. RTL simulation and the timing report never showed the fault. Checking the chip's answers did.
Then a logic analyzer on the busy pin: 186.000 µs per decision, which is 5,022 clocks at 27 MHz, exactly the RTL's count.
| default build | DSP on · carry on | ✗ 0 / 20 |
| -noalu | DSP on · carry off | ✗ same wrong bytes |
| -nodsp | LUT multipliers | ✓ 20 / 20 |
| -nodsp replay | every recorded decision | ✓ 4,000 / 4,000 |
| -nodsp closed loop | FPGA picks every action | ✓ 20 / 20 episodes |
Also built
Claude Code plugin · JavaScript
A hackathon harness: live research, an idea tournament scored against the event's rubric, a demo-first build with a separate QA judge, a mock judging panel, and a fact-checked write-up. A deadline clock runs throughout, and a human decides at three gates.
github.com/Jusman0/hackforge ↗
Arduino · forensics
An HC-SR04 alarm whose sketch was lost. I rebuilt it from a video of the serial monitor, down to the distance formula: the only common one that reproduces all 19 logged readings. A random formula would match about 1 time in 20,000.
github.com/Jusman0/ultrasonic-proximity-alarm ↗Simulation said it worked. Timing said it worked. The chip said otherwise. So now I check the chip.
About
I work where machine learning meets digital logic: I quantize networks to int8, write the Verilog that runs them, and prove the two agree.
Contact